1. Field of the Invention
This invention relates to flip chip technology, and more particularly, to a flip-chip bonding structure with stress-buffering property that can help prevent cracking and warpage of the flip-chip construction due to thermal stress.
2. Description of Related Art
The flip-chip technology is an advanced semiconductor fabrication technology that allows the overall package size to be made very compact. The flip-chip package configuration differs from conventional ones particularly in that the semiconductor chip is mounted in an upside-down manner on substrate and electrical coupled to the same by means of solder bumps provided on the active surface of the semiconductor chip. Since no bonding wires are required, the overall size of the flip-chip package can be made very compact as compared to conventional types of package configurations.
One drawback to conventional flip-chip bonding structure, however, is that under high-temperature conditions, such as during subsequent encapsulation process, the solder bump would be easily broken up due to thermal stress from the flip chip and substrate, which may impair the mechanical bonding and electrically coupling between the flip chip and the substrate, making the finished flip-chip package unreliable to use. This drawback is illustratively depicted in the following with reference to FIG. 1.
FIG. 1 is a schematic sectional diagram used to depict a conventional flip-chip bonding structure for bonding a flip chip 10 to a substrate 20. As shown, this flip-chip bonding structure includes an aluminum-based bond pad 11 over the active surface of the flip chip 10, a UBM (Under Bump Metallization) layer 12 over the aluminum-based bond pad 11, and a solder bump 13 over the UBM layer 12. Furthermore, the flip-chip bonding structure includes a copper-based bond pad 21 over the top surface of the substrate 20, and a solder-wettable metallization structure, such as a Cuxe2x80x94Nixe2x80x94Au metallization structure 22, over the copper-based bond pad 21.
The flip chip 10 is mounted in an upside-down manner over the substrate 20, with the solder bump 13 adhered to the Cuxe2x80x94Nixe2x80x94Au metallization structure 22, which allows the flip chip 10 to be mechanically bonded and electrically coupled to the substrate 20.
One drawback to the forgoing flip-chip bonding structure, however, is that under high-temperature conditions, such as during subsequent encapsulation process, the solder bump 13 would be easily broken up, which may impair the mechanical bonding and electrically coupling between the flip chip 10 and the substrate 20, making the finished flip-chip package unreliable to use. This is because that there is a CTE (coefficient of thermal expansion) mismatch between the flip chip 10 and the substrate 20, and that the aluminum-based bond pad 11 and the UBM layer 12 over the flip chip 10 as well as the copper-based bond pad 21 and the Cuxe2x80x94Nixe2x80x94Au metallization structure 22 over the substrate 20 are all highly rigid in material quality, thus allowing the thermal stress from the flip chip 10 and the substrate 20 to be straight transferred to the solder bump 13, causing a compressive force against the solder bump 13. As a result, the solder bump 13 would be easily broken up. Moreover, the thermal stress can cause cracking and warpage to the flip chip 10, the solder bump 13, and the substrate 20. If cracking of the solder bump 13 occurs, it may impair the mechanical bonding and electrically coupling between the flip chip 10 and the substrate 20, thus making the finished flip-chip package unreliable to use.
A great variety of patented technologies have been proposed for flip-chip, fabrication. A few of these patented technologies are listed in the following:
U.S. Pat. No. 5,904,859 entitled xe2x80x9cFLIP CHIP METALLIZATIONxe2x80x9d;
U.S. Pat. No. 5,902,686 entitled xe2x80x9cMETHODS FOR FORMING AN INTERMETALLIC REGION BETWEEN A SOLDER BUMP AND AN UNDER BUMP METALLURGY LAYER AND RELATED STRUCTURESxe2x80x9d;
U.S. Pat. No. 6,015,652 entitled xe2x80x9cMANUFACTURE OF FLIP-CHIP DEVICExe2x80x9d;
U.S. Pat. No. 5,137,845 entitled xe2x80x9cMETHOD OF FORMING METAL CONTACT PADS AND TERMINALS ON SEMICONDUCTOR CHIPSxe2x80x9d;
U.S. Pat. No. 5,173,359 entitled xe2x80x9cINTERCONNECTION SYSTEM AND METHOD OF FABRICATIONxe2x80x9d;
U.S. Pat. No. 5,736,456 entitled xe2x80x9cMETHOD OF FORMING CONDUCTIVE BUMPS ON DIE FOR FLIP CHIP APPLICATIONSxe2x80x9d;
U.S. Pat. No. 4,927,505 entitled xe2x80x9cMETALLIZATION SCHEME PROVIDING ADHESION AND BARRIER PROPERTIESxe2x80x9d;
U.S. Pat. No. 5,903,058 entitled xe2x80x9cCONDUCTIVE BUMPS ON DIE FOR FLIP CHIP APPLICATIONxe2x80x9d.
None of the above-listed patents, however, suggests a solution to the aforementioned thermal-stress problem in the flip-chip-bonding structure.
It is therefore an objective of this invention to provide a flip-chip bonding structure, which can help prevent cracking to the solder bumps due to thermal stress.
It is another objective of this invention to provide a flip-chip bonding structure, which can help prevent the flip-chip construction from warpage due to thermal stress.
It is still another objective of this invention to provide a flip-chip bonding structure, which allows the finished flip-chip package to be more assured in quality and reliability.
In accordance with the foregoing and other objectives, the invention proposes an improved flip-chip bonding structure with stress-buffering property that can help prevent cracking and warpage to the flip-chip construction due to thermal stress.
The flip-chip bonding structure of the invention comprises: (a) a chip-side bond pad formed over the flip chip; (b) a-first electrically-conductive stress-buffering layer laid over the chip-side bond pad; (c) a UBM layer laid over the first electrically-conductive stress-buffering layer; (d) a solder bump adhered to the UBM layer; (e) a substrate-side bond pad formed over the substrate; (f) a second electrically-conductive stress-buffering layer laid over the substrate-side bond pad; and (g) a solder-wettable metallization structure laid over the second electrically-conductive stress-buffering layer, and on which the solder bump is adhered.
The foregoing flip-chip bonding structure is characterized in the provision of the first electrically-conductive stress-buffering layer over the chip-side bond pad and the second electrically-conductive stress-buffering layer over the substrate-side bond pad, so that under high-temperature conditions, the thermal stress from the flip chip can be buffered by the first electrically-conductive stress-buffering-layer, while the thermal stress from the substrate can be buffered by the second electrically-conductive stress-buffering layer, thus allowing the flip-chip construction to be less likely subjected to cracking and warpage when undergoing high-temperature condition. The finished flip-chip package is therefore more assured in quality and reliability than the prior art.